1. Field of the Invention
The present invention generally relates to improving integrated circuit logic diagnostics by modeling physical layout information in the models used for diagnostic simulation and defect localization. An embodiment of the invention uses net connectivity information from integrated circuit layout to improve logic diagnostics and a heuristic method for determining when to include faults associated with clock or control signals in the fault candidate set for diagnostics.
2. Description of the Related Art
Modeling for test generation and diagnostic simulation uses logical test models, which model circuit logic and logical connectivity. Electrical behavior is typically modeled by stuck-at faults, transition faults or by adding patterns faults. Layout information may be indirectly included in the test netlist by customizing faults for a particular circuit. A physical defect mechanism can be mapped to electrical or logical behavior using default struck-at faults, pattern faults or composite faults. For example, mux circuits are often modeled by a mux primitive plus some pattern faults to get full coverage of the fail space for the circuit.
Gatemaker™ is an internal IBM® EDA tool. It may be used to create a gate level model directly from the layout to get accurate transistor level connections. Gatemaker™ improves the model to layout correspondence by better modeling the logic implementation. However, none of these methods include net structure in the model.
Diagnostics simulation, e.g., Cadence™ Encounter Test™, identifies a group of candidate faults that might explain the fail data from the chip being diagnosed. Test patterns are simulated for each fault and the resulting score is used to identify the faults most likely to explain the fail data. In the situation seen in FIG. 2, a net fans out to four downstream circuits, two fanouts pass test and two fanouts fail test. Current diagnostic simulation, using stuck-at faults, cannot identify a single fault which will explain this behavior.
Commercial diagnostics tools, (like the Cadence™ Encounter Test™), calculate scores for each fault candidate based on how many failing and passing measures are explained, or not explained by the particular fault. In the above example referring to FIG. 2, none of these faults would score perfectly; none of these faults would completely explain the fail data. Scores are used as a metric to identify chips for further analysis, rank candidate faults in the diagnostic callout, as well as to localize the faulty logic.